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gitea committed 2023-04-29 09:09:12 +08:00
1 parent 5e2e890cfc
commit 633d9b872b
1351 files changed
+730564
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MDK-ARM/EventRecorderStub.scvd
+9
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>
MDK-ARM/GB01VETx.uvguix.Administrator
+3866
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MDK-ARM/GB01VETx.uvguix.Memory
+2027
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MDK-ARM/GB01VETx.uvguix.zhang
+3718
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MDK-ARM/GB01VETx.uvoptx
+1148
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MDK-ARM/GB01VETx.uvprojx
+508
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<?xml version="1.0" encoding="UTF-8"?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>GB01VETx</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32G0B1VETx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32G0xx_DFP.1.4.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00024000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32G0Bx_512 -FS08000000 -FL080000 -FP0($$Device:STM32G0B1VETx$CMSIS\Flash\STM32G0Bx_512.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:STM32G0B1VETx$Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h</RegisterFile>
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<SFDFile>$$Device:STM32G0B1VETx$CMSIS\SVD\STM32G0B1.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>GB01VETx\</OutputDirectory>
<OutputName>GB01VETx</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>./GB01VETx/\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString />
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<ComprImg>0</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments>-REMAP</SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4101</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3 />
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
<RvctDeviceName />
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x24000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x24000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>5</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<Define>USE_HAL_DRIVER,STM32G0B1xx,CMSIS_device_header=&lt;stm32g0xx.h&gt;</Define>
<Undefine />
<IncludePath>../Core/Inc;../Drivers/STM32G0xx_HAL_Driver/Inc;../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32G0xx/Include;../Drivers/CMSIS/Include;../middleware/sfud/inc;../middleware/nr_micro_shell/inc;../middleware/xcmd/inc;../middleware/easyflash/inc;../App;../middleware/easylogger/inc;../Comm;../middleware/fifo;../middleware/at-command/include;../middleware/softimer;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM0;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls />
<Define />
<Undefine />
<IncludePath>..\Core\Inc</IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange />
<DataAddressRange />
<pXoBase />
<ScatterFile />
<IncludeLibs />
<IncludeLibsPath />
<Misc />
<LinkerInputFile />
<DisabledWarnings />
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group><GroupName>Application/User/Core</GroupName><Files><File><FileName>main.c</FileName><FileType>1</FileType><FilePath>../Core/Src/main.c</FilePath></File><File><FileName>gpio.c</FileName><FileType>1</FileType><FilePath>../Core/Src/gpio.c</FilePath></File><File><FileName>app_freertos.c</FileName><FileType>1</FileType><FilePath>../Core/Src/app_freertos.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads></FileArmAds></FileOption></File><File><FileName>adc.c</FileName><FileType>1</FileType><FilePath>../Core/Src/adc.c</FilePath></File><File><FileName>crc.c</FileName><FileType>1</FileType><FilePath>../Core/Src/crc.c</FilePath></File><File><FileName>dac.c</FileName><FileType>1</FileType><FilePath>../Core/Src/dac.c</FilePath></File><File><FileName>dma.c</FileName><FileType>1</FileType><FilePath>../Core/Src/dma.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads></FileArmAds></FileOption></File><File><FileName>iwdg.c</FileName><FileType>1</FileType><FilePath>../Core/Src/iwdg.c</FilePath></File><File><FileName>usart.c</FileName><FileType>1</FileType><FilePath>../Core/Src/usart.c</FilePath></File><File><FileName>rtc.c</FileName><FileType>1</FileType><FilePath>../Core/Src/rtc.c</FilePath></File><File><FileName>spi.c</FileName><FileType>1</FileType><FilePath>../Core/Src/spi.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads></FileArmAds></FileOption></File><File><FileName>tim.c</FileName><FileType>1</FileType><FilePath>../Core/Src/tim.c</FilePath></File><File><FileName>wwdg.c</FileName><FileType>1</FileType><FilePath>../Core/Src/wwdg.c</FilePath></File><File><FileName>stm32g0xx_it.c</FileName><FileType>1</FileType><FilePath>../Core/Src/stm32g0xx_it.c</FilePath></File><File><FileName>stm32g0xx_hal_msp.c</FileName><FileType>1</FileType><FilePath>../Core/Src/stm32g0xx_hal_msp.c</FilePath></File><File><FileName>stm32g0xx_hal_timebase_tim.c</FileName><FileType>1</FileType><FilePath>../Core/Src/stm32g0xx_hal_timebase_tim.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OLine truncated
<Group>
<GroupName>midderware/sfud</GroupName>
<Files>
<File>
<FileName>sfud.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\sfud\src\sfud.c</FilePath>
</File>
<File>
<FileName>sfud_sfdp.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\sfud\src\sfud_sfdp.c</FilePath>
</File>
<File>
<FileName>sfud_port.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\sfud\port\sfud_port.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>midderware/easyfalsh</GroupName>
<Files>
<File>
<FileName>easyflash.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easyflash\src\easyflash.c</FilePath>
</File>
<File>
<FileName>ef_env.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easyflash\src\ef_env.c</FilePath>
</File>
<File>
<FileName>ef_iap.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easyflash\src\ef_iap.c</FilePath>
</File>
<File>
<FileName>ef_log.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easyflash\src\ef_log.c</FilePath>
</File>
<File>
<FileName>ef_utils.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easyflash\src\ef_utils.c</FilePath>
</File>
<File>
<FileName>ef_port.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easyflash\port\ef_port.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>midderware/easylogger</GroupName>
<Files>
<File>
<FileName>elog.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easylogger\src\elog.c</FilePath>
</File>
<File>
<FileName>elog_utils.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easylogger\src\elog_utils.c</FilePath>
</File>
<File>
<FileName>elog_port.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\easylogger\port\elog_port.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>midderware/softimer</GroupName>
<Files>
<File>
<FileName>softimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\middleware\softimer\softimer.c</FilePath>
</File>
</Files>
</Group>
<Group><GroupName>Drivers/CMSIS</GroupName><Files><File><FileName>startup_stm32g0b1xx.s</FileName><FileType>2</FileType><FilePath>.\startup_stm32g0b1xx.s</FilePath></File><File><FileName>system_stm32g0xx.c</FileName><FileType>1</FileType><FilePath>../Core/Src/system_stm32g0xx.c</FilePath></File></Files></Group>
<Group><GroupName>Drivers/STM32G0xx_HAL_Driver</GroupName><Files><File><FileName>stm32g0xx_hal_adc.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c</FilePath></File><File><FileName>stm32g0xx_hal_adc_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c</FilePath></File><File><FileName>stm32g0xx_ll_adc.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c</FilePath></File><File><FileName>stm32g0xx_hal_rcc.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c</FilePath></File><File><FileName>stm32g0xx_hal_rcc_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c</FilePath></File><File><FileName>stm32g0xx_ll_rcc.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c</FilePath></File><File><FileName>stm32g0xx_hal_flash.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c</FilePath></File><File><FileName>stm32g0xx_hal_flash_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c</FilePath></File><File><FileName>stm32g0xx_hal_gpio.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c</FilePath></File><File><FileName>stm32g0xx_hal_dma.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c</FilePath></File><File><FileName>stm32g0xx_hal_dma_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c</FilePath></File><File><FileName>stm32g0xx_ll_dma.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c</FilePath></File><File><FileName>stm32g0xx_hal_pwr.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c</FilePath></File><File><FileName>stm32g0xx_hal_pwr_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c</FilePath></File><File><FileName>stm32g0xx_hal_cortex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c</FilePath></File><File><FileName>stm32g0xx_hal.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c</FilePath></File><File><FileName>stm32g0xx_hal_exti.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c</FilePath></File><File><FileName>stm32g0xx_hal_crc.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c</FilePath></File><File><FileName>stm32g0xx_hal_crc_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c</FilePath></File><File><FileName>stm32g0xx_hal_dac.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c</FilePath></File><File><FileName>stm32g0xx_hal_dac_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c</FilePath></File><File><FileName>stm32g0xx_hal_iwdg.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c</FilePath></File><File><FileName>stm32g0xx_hal_uart.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c</FilePath></File><File><FileName>stm32g0xx_hal_uart_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c</FilePath></File><File><FileName>stm32g0xx_hal_rtc.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c</FilePath></File><File><FileName>stm32g0xx_hal_rtc_ex.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c</FilePath></File><File><FileName>stm32g0xx_hal_spi.c</FileName><FileType>1</FileType><FilePath>../Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn>Line truncated
<Group>
<GroupName>Board</GroupName>
</Group>
<Group><GroupName>Middlewares/FreeRTOS</GroupName><GroupOption><CommonProperty><UseCPPCompiler>0</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>2</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><GroupArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>4</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads><Aads><interw>2</interw><Ropi>2</Ropi><Rwpi>2</Rwpi><thumb>2</thumb><SplitLS>2</SplitLS><SwStkChk>2</SwStkChk><NoWarn>2</NoWarn><uSurpInc>2</uSurpInc><useXO>2</useXO><ClangAsOpt>0</ClangAsOpt></Aads></GroupArmAds></GroupOption><Files><File><FileName>croutine.c</FileName><FileType>1</FileType><FilePath>../Middlewares/Third_Party/FreeRTOS/Source/croutine.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads></FileArmAds></FileOption></File><File><FileName>event_groups.c</FileName><FileType>1</FileType><FilePath>../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads></FileArmAds></FileOption></File><File><FileName>list.c</FileName><FileType>1</FileType><FilePath>../Middlewares/Third_Party/FreeRTOS/Source/list.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainCh>2</PlainCh><Ropi>2</Ropi><Rwpi>2</Rwpi><wLevel>0</wLevel><uThumb>2</uThumb><uSurpInc>2</uSurpInc><uC99>2</uC99><uGnu>2</uGnu><useXO>2</useXO><v6Lang>0</v6Lang><v6LangP>0</v6LangP><vShortEn>2</vShortEn><vShortWch>2</vShortWch><v6Lto>2</v6Lto><v6WtE>2</v6WtE><v6Rtti>2</v6Rtti></Cads></FileArmAds></FileOption></File><File><FileName>queue.c</FileName><FileType>1</FileType><FilePath>../Middlewares/Third_Party/FreeRTOS/Source/queue.c</FilePath><FileOption><CommonProperty><UseCPPCompiler>2</UseCPPCompiler><RVCTCodeConst>0</RVCTCodeConst><RVCTZI>0</RVCTZI><RVCTOtherData>0</RVCTOtherData><ModuleSelection>0</ModuleSelection><IncludeInBuild>1</IncludeInBuild><AlwaysBuild>2</AlwaysBuild><GenerateAssemblyFile>2</GenerateAssemblyFile><AssembleAssemblyFile>2</AssembleAssemblyFile><PublicsOnly>2</PublicsOnly><StopOnExitCode>11</StopOnExitCode><ComprImg>1</ComprImg></CommonProperty><FileArmAds><Cads><interw>2</interw><Optim>0</Optim><oTime>2</oTime><SplitLS>2</SplitLS><OneElfS>2</OneElfS><Strict>2</Strict><EnumInt>2</EnumInt><PlainLine truncated
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.4.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0" />
<targetInfos>
<targetInfo name="GB01VETx" />
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" condition="STM32G0B1 ARMCC" name="Drivers\CMSIS\Device\ST\STM32G0xx\Source\Templates\arm\startup_stm32g0b1xx.s" version="1.4.0">
<instance index="0" removed="1">RTE\Device\STM32G0B1VETx\startup_stm32g0b1xx.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.4.0" condition="STM32G0 CMSIS" />
<package name="STM32G0xx_DFP" schemaVersion="1.7.1" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0" />
<targetInfos />
</file>
<file attr="config" category="source" name="Drivers\CMSIS\Device\ST\STM32G0xx\Source\Templates\system_stm32g0xx.c" version="1.4.0">
<instance index="0" removed="1">RTE\Device\STM32G0B1VETx\system_stm32g0xx.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.4.0" condition="STM32G0 CMSIS" />
<package name="STM32G0xx_DFP" schemaVersion="1.7.1" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0" />
<targetInfos />
</file>
</files>
</RTE>
</Project>
MDK-ARM/JLinkLog.txt
+12798
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File diff suppressed because it is too large. Load diff
MDK-ARM/JLinkSettings.ini
+42
View File
@@ -0,0 +1,42 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
[RAM]
VerifyDownload = 0x00
MDK-ARM/RTE/Device/STM32G0B1VETx/.startup_stm32g0b1xx.s@1.4.0
+252
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@@ -0,0 +1,252 @@
;******************************************************************************
;* File Name : startup_stm32g0b1xx.s
;* Author : MCD Application Team
;* Description : STM32G0b1xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under Apache License, Version 2.0,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/Apache-2.0
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_CRS_IRQHandler ; RCC & CRS
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD USB_UCPD1_2_IRQHandler ; USB, UCPD1 & UCPD2
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 ,DMAMUX1 overrun
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4
DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1
DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0
DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_3_IRQHandler ; I2C2, I2C3
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_3_IRQHandler ; SPI2, SPI3
DCD USART1_IRQHandler ; USART1
DCD USART2_LPUART2_IRQHandler ; USART2 & LPUART2
DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1
DCD CEC_IRQHandler ; CEC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
EXPORT RTC_TAMP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_CRS_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT USB_UCPD1_2_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_TIM4_IRQHandler [WEAK]
EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK]
EXPORT TIM7_LPTIM2_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_FDCAN_IT0_IRQHandler [WEAK]
EXPORT TIM17_FDCAN_IT1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_3_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_LPUART2_IRQHandler [WEAK]
EXPORT USART3_4_5_6_LPUART1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_VDDIO2_IRQHandler
RTC_TAMP_IRQHandler
FLASH_IRQHandler
RCC_CRS_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
USB_UCPD1_2_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler
ADC1_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_TIM4_IRQHandler
TIM6_DAC_LPTIM1_IRQHandler
TIM7_LPTIM2_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_FDCAN_IT0_IRQHandler
TIM17_FDCAN_IT1_IRQHandler
I2C1_IRQHandler
I2C2_3_IRQHandler
SPI1_IRQHandler
SPI2_3_IRQHandler
USART1_IRQHandler
USART2_LPUART2_IRQHandler
USART3_4_5_6_LPUART1_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
MDK-ARM/RTE/Device/STM32G0B1VETx/.system_stm32g0xx.c@1.4.0
+290
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@@ -0,0 +1,290 @@
/**
******************************************************************************
* @file system_stm32g0xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32g0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB Prescaler | 1
*-----------------------------------------------------------------------------
* HSI Division factor | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* Require 48MHz for RNG | Disabled
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx_system
* @{
*/
/** @addtogroup STM32G0xx_System_Private_Includes
* @{
*/
#include "stm32g0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000UL;
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
*
* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp;
uint32_t pllvco;
uint32_t pllr;
uint32_t pllsource;
uint32_t pllm;
uint32_t hsidiv;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_0: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
SystemCoreClock = LSI_VALUE;
break;
case RCC_CFGR_SWS_2: /* LSE used as system clock */
SystemCoreClock = LSE_VALUE;
break;
case RCC_CFGR_SWS_1: /* PLL used as system clock */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
{
pllvco = (HSE_VALUE / pllm);
}
else /* HSI used as PLL clock source */
{
pllvco = (HSI_VALUE / pllm);
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
SystemCoreClock = pllvco/pllr;
break;
case 0x00000000U: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
SystemCoreClock = (HSI_VALUE/hsidiv);
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
MDK-ARM/RTE/Device/STM32G0B1VETx/startup_stm32g0b1xx.s
+252
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@@ -0,0 +1,252 @@
;******************************************************************************
;* File Name : startup_stm32g0b1xx.s
;* Author : MCD Application Team
;* Description : STM32G0b1xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under Apache License, Version 2.0,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/Apache-2.0
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_CRS_IRQHandler ; RCC & CRS
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD USB_UCPD1_2_IRQHandler ; USB, UCPD1 & UCPD2
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 ,DMAMUX1 overrun
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4
DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1
DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0
DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_3_IRQHandler ; I2C2, I2C3
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_3_IRQHandler ; SPI2, SPI3
DCD USART1_IRQHandler ; USART1
DCD USART2_LPUART2_IRQHandler ; USART2 & LPUART2
DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1
DCD CEC_IRQHandler ; CEC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
EXPORT RTC_TAMP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_CRS_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT USB_UCPD1_2_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_TIM4_IRQHandler [WEAK]
EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK]
EXPORT TIM7_LPTIM2_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_FDCAN_IT0_IRQHandler [WEAK]
EXPORT TIM17_FDCAN_IT1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_3_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_LPUART2_IRQHandler [WEAK]
EXPORT USART3_4_5_6_LPUART1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_VDDIO2_IRQHandler
RTC_TAMP_IRQHandler
FLASH_IRQHandler
RCC_CRS_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
USB_UCPD1_2_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler
ADC1_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_TIM4_IRQHandler
TIM6_DAC_LPTIM1_IRQHandler
TIM7_LPTIM2_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_FDCAN_IT0_IRQHandler
TIM17_FDCAN_IT1_IRQHandler
I2C1_IRQHandler
I2C2_3_IRQHandler
SPI1_IRQHandler
SPI2_3_IRQHandler
USART1_IRQHandler
USART2_LPUART2_IRQHandler
USART3_4_5_6_LPUART1_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
MDK-ARM/RTE/Device/STM32G0B1VETx/system_stm32g0xx.c
+290
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@@ -0,0 +1,290 @@
/**
******************************************************************************
* @file system_stm32g0xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32g0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB Prescaler | 1
*-----------------------------------------------------------------------------
* HSI Division factor | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* Require 48MHz for RNG | Disabled
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx_system
* @{
*/
/** @addtogroup STM32G0xx_System_Private_Includes
* @{
*/
#include "stm32g0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000UL;
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
*
* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp;
uint32_t pllvco;
uint32_t pllr;
uint32_t pllsource;
uint32_t pllm;
uint32_t hsidiv;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_0: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
SystemCoreClock = LSI_VALUE;
break;
case RCC_CFGR_SWS_2: /* LSE used as system clock */
SystemCoreClock = LSE_VALUE;
break;
case RCC_CFGR_SWS_1: /* PLL used as system clock */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
{
pllvco = (HSE_VALUE / pllm);
}
else /* HSI used as PLL clock source */
{
pllvco = (HSI_VALUE / pllm);
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
SystemCoreClock = pllvco/pllr;
break;
case 0x00000000U: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
SystemCoreClock = (HSI_VALUE/hsidiv);
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
MDK-ARM/RTE/_GB01VETx/RTE_Components.h
+21
View File
@@ -0,0 +1,21 @@
␍
/*␍
* Auto generated Run-Time-Environment Configuration File␍
* *** Do not modify ! ***␍
*␍
* Project: 'GB01VETx' ␍
* Target: 'GB01VETx' ␍
*/␍
␍
#ifndef RTE_COMPONENTS_H␍
#define RTE_COMPONENTS_H␍
␍
␍
/*␍
* Define the Device Header File: ␍
*/␍
#define CMSIS_device_header "stm32g0xx.h"␍
␍
␍
␍
#endif /* RTE_COMPONENTS_H */␍
MDK-ARM/startup_stm32g0b1xx.s
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;******************************************************************************
;* File Name : startup_stm32g0b1xx.s
;* Author : MCD Application Team
;* Description : STM32G0b1xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under Apache License, Version 2.0,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/Apache-2.0
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_CRS_IRQHandler ; RCC & CRS
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD USB_UCPD1_2_IRQHandler ; USB, UCPD1 & UCPD2
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 ,DMAMUX1 overrun
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4
DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1
DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0
DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_3_IRQHandler ; I2C2, I2C3
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_3_IRQHandler ; SPI2, SPI3
DCD USART1_IRQHandler ; USART1
DCD USART2_LPUART2_IRQHandler ; USART2 & LPUART2
DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1
DCD CEC_IRQHandler ; CEC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
EXPORT RTC_TAMP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_CRS_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT USB_UCPD1_2_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_TIM4_IRQHandler [WEAK]
EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK]
EXPORT TIM7_LPTIM2_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_FDCAN_IT0_IRQHandler [WEAK]
EXPORT TIM17_FDCAN_IT1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_3_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_LPUART2_IRQHandler [WEAK]
EXPORT USART3_4_5_6_LPUART1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_VDDIO2_IRQHandler
RTC_TAMP_IRQHandler
FLASH_IRQHandler
RCC_CRS_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
USB_UCPD1_2_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler
ADC1_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_TIM4_IRQHandler
TIM6_DAC_LPTIM1_IRQHandler
TIM7_LPTIM2_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_FDCAN_IT0_IRQHandler
TIM17_FDCAN_IT1_IRQHandler
I2C1_IRQHandler
I2C2_3_IRQHandler
SPI1_IRQHandler
SPI2_3_IRQHandler
USART1_IRQHandler
USART2_LPUART2_IRQHandler
USART3_4_5_6_LPUART1_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****